About me

I'm Phuc; I'm pursuing B.S. in Cybersecurity Engineering at University of Cincinnati. I love playing piano, video games and capturing pictures of life.

Currently, I'm doing research at Dr. Boyang Wang's lab at University of Cincinnati, working on pre-silicon Side-channel Analysis on AES 128-bit ECB encryption, particularly High Level Synthesis and Hardware (Verilog), and Fault Injection at RTL level.

I have experience with reverse engineering and malware analysis using IDA, Ghidra, x64dbg, PE editor, PE bear. I also have experience with malware development using technique like DLL injection, thread hijacking, function hooking, Linux process injection with ptrace. I also have had sometime doing DFIR through practical labs. I also have extensive experience working with Vivado and Verilog design for FPGA.

During Summer 2024, I had an opportunity working with Viettel Cyber Security, where I had sometime doing log collection on customer's internal server for threat hunting operation later on. I also had a chance to watch operation in SOC, and learn about what's going on in real life industry. It was such amazing experience.

Publications:

  1. Logan Reichling, Ryan Evans, Mabon Ninan, Phuc Mai, Boyang Wang, Yunsi Fei, and John M. Emmert, "MicroPower: Micro Neural Networks for Side-Channel Attacks," IEEE International Symposium on Hardware Oriented Security and Trust (HOST 2025), San Jose, May 5-8, 2025

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